1. Field of the Invention
The present invention relates to a reference voltage circuit for generating a constant reference voltage.
2. Description of the Related Art
FIG. 12 shows the conventional ED type reference voltage circuit.
The ED type reference voltage circuit includes a depletion NMOS transistor 84 and an NMOS transistor 85. The gate and source of the depletion NMOS transistor 84 are connected with the reference voltage output terminal 83 and the drain thereof is connected with the power supply terminal 81. The gate and drain of the NMOS transistor 85 are connected with the reference voltage output terminal 83 and the source thereof is connected with the ground terminal 82 (see, for example, JP 04-065546 B (FIG. 2)).
According to the ED type reference voltage circuit, even when a power supply voltage of the power supply terminal 81 varies, a reference voltage of the ED type reference voltage circuit 86 does not easily vary while each of the NMOS transistors operates in saturation.
Assume that a mutual conductance of the NMOS transistor 85 is expressed by gm85 and an output resistance of the depletion NMOS transistor 84 is expressed by ro84. In this case, a power supply rejection ratio (ratio between variation in power supply voltage and variation in reference voltage due to variation in power supply voltage) PSRRLF in the reference voltage output terminal 83 at low frequency is calculated by the following expression.PSRRLF=gm85×ro84  (2)
However, because of, for example, a channel length modulation effect of the depletion NMOS transistor 84, when the power supply voltage of the power supply terminal 81 varies, the reference voltage of the ED type reference voltage circuit 86 also varies. Therefore, the power supply rejection ratio PSRRLF does not become larger.
In order to take measures against such a situation, there is a case where a cascode circuit is added to the power supply terminal 81. FIG. 13 shows a conventional reference voltage circuit.
This reference voltage circuit includes a bias voltage supplying circuit 89, an NMOS transistor 88, and the ED type reference voltage circuit 86. The gate of the NMOS transistor 88 is connected with the bias voltage supplying circuit 89, the source thereof is connected with the ED type reference voltage circuit 86, and the drain thereof is connected with the power supply terminal 87.
According to the reference voltage circuit, even when a power supply voltage of the power supply terminal 87 varies, the reference voltage of the ED type reference voltage circuit 86 does not easily vary because the NMOS transistor 88 operates such that the power supply voltage of the power supply terminal 81 is constant.
Assume that a mutual conductance of the NMOS transistor 88 is expressed by gm88, a substrate bias mutual conductance of the NMOS transistor 88 is expressed by gmb88, and an output resistance of the NMOS transistor 88 is expressed by ro88. In this case, the power supply rejection ratio PSRRLF in the reference voltage output terminal 83 at low frequency is calculated by the following expression.PSRRLF={(gm88+gmb88)×ro88}×(gm85×ro84)  (3)In other words, the power supply rejection ratio PSRRLF is multiplied by “(gm88+gmb88)×ro88”.
An application example of the reference voltage circuit will be described. FIG. 14 shows an application example of the conventional reference voltage circuit.
This reference voltage circuit includes depletion NMOS transistors 91 to 93, an NMOS transistor 94, the reference voltage output terminal 83, and the ED type reference voltage circuit 86. The gate of the depletion NMOS transistor 91 is connected with the source of the depletion NMOS transistor 92, the source thereof is connected with the ED type reference voltage circuit 86, and the drain thereof is connected with the power supply terminal 87. The gate of the depletion NMOS transistor 92 is connected with the source of the depletion NMOS transistor 91, the source thereof is connected with the drain of the depletion NMOS transistor 93, and the drain thereof is connected with the power supply terminal 87. The gate of the depletion NMOS transistor 93 is connected with the source thereof. The gate of the NMOS transistor 94 is connected with the drain thereof and the source of the depletion NMOS transistor 93. The source of the NMOS transistor 94 is connected with the ground terminal 82 (see, for example, JP 2003-295957 A (FIG. 1)).
According to the reference voltage circuit, even when the power supply voltage of the power supply terminal 87 varies, the reference voltage of the ED type reference voltage circuit 86 does not easily vary because the depletion NMOS transistor 91 operates such that the power supply voltage of the power supply terminal 81 is constant.
When the depletion NMOS transistor 92 operates such that a gate voltage of the depletion NMOS transistor 91 is equal to a source voltage thereof, a mutual conductance of the depletion NMOS transistor 91 does not contribute to the power supply rejection ratio. Therefore, assume that a substrate bias mutual conductance of the depletion NMOS transistor 91 is expressed by gmb91 and an output resistance of the depletion NMOS transistor 91 is expressed by ro91. In this case, the power supply rejection ratio PSRRLF in the reference voltage output terminal 83 at low frequency is calculated by the following expression.PSRRLF=(gmb91×ro91)×(gm85×ro84)  (4)In other words, the power supply rejection ratio PSRRLF is multiplied by “gmb91×ro91”.
However, when the power supply voltage of the power supply terminal 87 lowers and thus the depletion NMOS transistor 91 operates in non-saturation, the output resistance ro91 of the depletion NMOS transistor 91 becomes smaller to reduce the power supply rejection ratio PSRRLF. 